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RM0008
Basic timers (TIM6&TIM7)
Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It
is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register).
It can be changed on the fly as the TIMx_PSC control register is buffered. The new
prescaler ratio is taken into account at the next update event.
Figure 146 and Figure 147 give some examples of the counter behavior when the prescaler
ratio is changed on the fly.
Figure 146. Counter timing diagram with prescaler division change from 1 to 2
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
F7
F8 F9 FA FB F C
00
01
02
03
Update event (UEV)
Prescaler control register
0
1
Write a new value in TIMx_PSC
Prescaler buffer
0
1
Prescaler counter
0
0
1
0
1
0
1
0
1
Figure 147. Counter timing diagram with prescaler division change from 1 to 4
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
F7
F8 F9 FA FB F C
00
01
Update event (UEV)
Prescaler control register
0
3
Write a new value in TIMx_PSC
Prescaler buffer
0
3
Prescaler counter
0
0
1
2
3
0
1
2
3
Doc ID 13902 Rev 9
377/995
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